1. Technical Field
This disclosure relates to electronic design automation (EDA). More specifically, this disclosure relates to parasitic extraction for via arrays during post-layout simulation.
2. Related Art
A via array is a group of vias arranged in a regular pattern of rows and columns but used as a single via to connect two nets. Via arrays exist in many types of circuits to provide redundancy, and to improve yield and reliability. Depending on how parasitics are extracted for the via array, the extraction can have a significant impact on the size and accuracy of the parasitic netlist and on the post-layout simulation runtime.
Existing extraction tools have many shortcomings. Existing extraction tools do not preserve point-to-point resistance when all vias in a via array are merged together. Existing extraction tools may produce large networks. Further, existing extraction tools may not be deterministic, i.e., they may produce different extracted resistance values in different runs, which can lead to inconsistency in simulation results.